I. Field of the Disclosure
The technology of the disclosure relates generally to instruction pipelining in processors, and more particularly to re-using previously decoded instructions of recently-provided instructions to be executed by a processor.
II. Background
Instruction pipelining is a processing technique whereby the throughput of computer instructions being executed by a processor may be increased. In this regard, the handling of each instruction is split into a series of steps as opposed to each instruction being processed sequentially and fully executed before processing a next instruction. These steps are executed in an instruction pipeline composed of multiple stages. There are several cycles between the time at which an instruction is fetched from memory until the time at which the instruction is actually executed as the instruction flows through various pipeline stages of an instruction pipeline.
Conventionally, the instruction pipeline decodes an instruction after the instruction is fetched in the previous step. An instruction is decoded into a series of shorter operations known as micro-operations or micro-ops. Decoding instructions in this manner causes the instruction pipeline to execute the shorter micro-ops instead of the more complex instructions, which helps to improve instruction pipeline performance. If a processor accesses a particular pattern of instructions multiple times, the instruction pipeline may perform the same fetch and decode steps each time the same pattern of instructions is accessed. In this manner, processors may employ dedicated storage that is configured to store the micro-ops generated when decoding a pattern of instructions. If the processor is instructed to access a pattern of instructions from a given fetch address, the processor may search the dedicated storage for the micro-ops corresponding to the fetch address. If the micro-ops have been previously decoded and stored in the dedicated storage, the micro-ops may be retrieved and supplied from the dedicated storage to the processor, thus avoiding the need to re-fetch and re-decode the pattern of instructions. In this manner, supplying the micro-ops from the dedicated storage rather than through fetching and decoding allows the fetch and decode steps to be temporarily disabled, thus reducing power consumption.
While supplying previously decoded micro-ops from dedicated storage reduces power consumption by temporarily disabling fetching and decoding, retrieving and passing the micro-ops causes corresponding power consumption. For example, the micro-ops are retrieved from the dedicated storage and passed to the processor such that the micro-ops are executed according to the timing of the instruction pipeline. In particular, in response to retrieving micro-ops from the dedicated storage, these micro-ops are passed to corresponding queues in the instruction pipeline until they can be provided to subsequent stages for execution. Thus, it would be advantageous to avoid re-fetching and re-decoding previously decoded instructions while also reducing power consumption corresponding to retrieving and passing micro-ops through an instruction pipeline.